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dcl 12s0a 0s 2 0n fa ds_ dc l 12s0a 0s 2 0n fa _ 1115 20 12 e - mail : dcdc @ d elta.com.tw http://www.deltaww.com/dcdc p1 features ? high efficiency: 9 3 % @ 12 vin, 5 v/ 2 0 a out 9 2 % @ 12 vin, 3.3 v/ 2 0 a out 90 % @ 12 vin, 2.5 v/ 2 0 a out 89 % @ 12 vin, 1.8 v/ 2 0 a out 83 % @ 12 vin, 1.2 v/ 2 0 a out 79 % @ 1 0 vin, 0.69 v/ 2 0 a out ? small size and low profile: 33.02 x 13.46 x 8.5 mm ( 1.3 x 0.53x 0. 33 ) ? surface mount packaging ? standard footprint ? voltage and resistor - based trim ? pre - bias startup ? output voltage tracking ? no minimum load required ? output voltage programmable from ? 0. 69 vdc to 5 vdc via external resistor ? fixed frequency operation and ablity to synchronize with external clock ? input uvlo, output ocp ? remote on/off ? iso 9001, tl 9000, iso 14001, qs9000, ohsas18001 certified manufacturing facility ul/cul 60950 - 1 (us & canada) ? ce mark meets 73/23/eec and 93/68/eec directives delphi d c l , non - isolated point of load dc/dc power modules : 4.5~14 vin, 0.69 v - 5 v/ 2 0 aout the delphi series dcl , 4.5 - 14 v input, single output, non - isolated point of load dc/dc converters are the latest offering from a world leader in power systems technology and manufacturing -- delta electronics, inc. the d cl seri es provides a programmable output voltage from 0. 69 v to 5 v using an external resistor and has flexible and programmable tracking features to enable a variety of startup voltages as well as tracking between power modules. this product family is available in surface mount and provides up to 20 a of output current in an industry standard footprint. with creative design technology and optimization of component placement, these converters possess outstanding electrical and thermal performance, as well as extrem ely high reliability under highly stressful operating conditions. options ? negative /positive on/off logic ? vo t racking feature applications ? t elecom / datacom ? distributed power architectures ? servers and workstations ? lan / wan applications ? data processing applications
ds_ d cl 12s0a 0s 2 0n fa _11152012 e - mail : dcdc @ d elta.com.tw http://www.deltaww.com/dcdc p 2 technical specificat ions parameter notes and conditions dc l 12s0a0s 2 0 n fa min. typ. max. units absolute maximum ratings input voltage (continuous) - 0.3 15 v sequencing voltage - 0.3 vin max v ope rating ambient tem perature - 40 85 storage temperature - 55 125 input characteristics operating input voltage vo Q vin C 0.6 4.5 14 v input under - voltage lockout turn - on voltage threshold 4.45 v turn - off voltage threshold 4.2 v lockout hysteresis voltage 0.25 v maximum input current vin=4.5v to14v, io=io,max 20 a no - load input current ( i o = 0, module enabled) vin= 10v, vo,set = 0.6 9 vdc 6 0 ma vin= 12v, vo,set = 3.3 vdc 74 ma off converter input current (vin = 12.0vdc, module disabled) 3 ma inru sh transient 1 a2s input reflected ripple current, peak - to - peak (5hz to 20mhz, 1h source impedance; vin =0 to 14 v, io= iomax ; 43 map - p input ripple rejection(120hz) 45 db output characteristics output voltage set point with 0.5% tolerance for external resistor used to set output voltage) - 1.5 vo,set +1.5 %vo,set output voltage adjustable range (selected by an external resistor) 0. 6 9 5.0 v output voltage regulation line(vin=vin, min to vin, max) for vo>=2.5v 0.4 %vo,set vo,set for vo<2.5v 10 mv load(io=io, min to io, max) for vo>=2.5v 10 mv f or vo<2.5v 5 mv temperature(tref=ta, min to ta, max) for vo>=2.5v 0. 5 %vo,set vo,set for vo<2.5v 5 mv total output voltage range over sample load, line and temperature - 2.5 + 2.5 %vo,set output voltage ripple and noise 5hz to 20mhz bandwidth peak - to - peak vin= vin nominal, io=io,min to io,max , co= 1f+10uf ceramic, 80 mv rms vin= vin nominal, io=io,min to io,max, co= 1f+10uf ceramic, 28 mv output current range 0 2 0 a output voltage over - shoot at start - up 5 % vo,set output dc current - limit inception 1 40 % io output short - circuit current (hiccup mode) io,s/c 2 .6 adc dynamic characteristics dynamic load response 10f tan & 1f ceramic load cap, 2.5a/s positive step change in output current 50% io, max to 100% io, max 38 0 mv negative step change in output current 100% io, max to 50% io, max 380 mv settling time to 10% of peak deviation 3 0 s turn - on transient io=io.max start - up time, from on/off control time for von/off to vo=10% of vo,set 2 ms start - up time, from input time for vin=vin,min to vo=10% of vo,set 2 ms output voltage rise time time for vo to rise from 10% to 90% of vo,set 5 ms output capacitive load full load; esr R 0.15 m 94 10 00 f efficiency vo=5.0v vin=12v, 100% load 93 % vo= 3.3 v vin=12v, 100% load 92 % vo= 2.5 v vin=12v, 100% load 90 % vo =1.8 v vin=12v, 100% load 89 % vo= 1.2 v vin=12v, 100% load 83 % vo =0.69 v vin= 10 v, 100% load 79 % featur e characteristics switching frequency 5 00 khz synchronization frequency range 520 600 khz on/off control, (negative logic) logic low voltage module on, von/off 0 1 v logic high voltage module off, von/off 2 vin,max v logic low curre nt module on, ion/off 10 a logic high current module off, ion/off 1 ma on/off control, (positive logic) logic high voltage module on, von/off vin - 1 vin,max v logic low voltage module off, von/off 3.5 v logic low current module on, ion/o ff 3 ma logic high current module off, ion/off 25 a tracking slew rate capability 0.5 v/msec tracking delay time delay from vin.min to application of tracking voltage 10 ms tracking accuracy power - up 0.5 v/ms 100 mv power - down 0.5 v/ms 1 5 0 mv general specifications mtbf io=80% of io, max; ta=25c 32.51 m hours weight 5.5 grams (t a = 25c, airflow rate = 300 lfm, v in = 4.5 vdc and 14.0 vdc, nominal vout unless otherwise noted.)
ds_ d cl 12s0a 0s 2 0n fa _11152012 e - mail : dcdc @ d elta.com.tw http://www.deltaww.com/dcdc p 3 electrical character istics curves figure 1: converter efficiency vs. output current ( v out = 0.69v ) figure 2: converter efficiency vs. output curre nt ( 1.2 v out) figure 3: converter efficiency vs. output current ( 1.8 v out) figure 4: converter efficiency vs. output current ( 2.5 v out) figure 5 : converter efficiency vs. output current 3.3 v out) figure 6 : converter efficiency v s. output current ( 5.0 v out)
ds_ d cl 12s0a 0s 2 0n fa _11152012 e - mail : dcdc @ d elta.com.tw http://www.deltaww.com/dcdc p 4 electrical character istics curves (con.) figure 7 : output ripple & noise at 7 vin, 0.69 v/ 2 0 a out ch1:vout, 20mv/div, 1us/div figure 8 : output ripple & noise at 12 vin, 1.8 v/ 2 0 a ou t ch1:vout, 20mv/div, 1us/div figure 9 : output ripple & noise at 12 vin, 3.3 v/ 2 0 a out ch1:vout, 20mv/div, 1us/div figure 10 : output ripple & noise at 12 vin, 5.0 v/ 2 0 a ou t ch1:vout, 20mv/div, 1us/div
ds_ d cl 12s0a 0s 2 0n fa _11152012 e - mail : dcdc @ d elta.com.tw http://www.deltaww.com/dcdc p 5 electrical character istics curves (con.) figure 11 : turn on delay time at 7 vin, 0.69 v/ 2 0 a out. ( green : vout, 0.5v/div, yellow : vin, 2v/div . 2ms/div ) ( yellow : vout, 0.2v/div, green : vin, 5v/div . 2ms/div ) figure 1 2 : turn on delay time at 12 vin, 1.8 v/ 2 0 a out. ( green : vout, 0.5v/div, yellow : vin, 5v/div . 2ms/div ) figure 1 3 : turn on delay time at 12 vin, 3.3 v/ 2 0 a out . ( green : vout, 1v/div, yellow : vin, 5v/div . 2ms/div ) figure 1 4 : turn on delay time at 12 vin, 5.0 v/ 2 0 a out . ( green : vout, 2v/div, yellow : vin, 5v/div . 2ms/div )
ds_ d cl 12s0a 0s 2 0n fa _11152012 e - mail : dcdc @ d elta.com.tw http://www.deltaww.com/dcdc p 6 electrical charact eristics curves (con .) figure 1 5 : turn on delay time at remote on 7 vin, 0.69 v/ 2 0 a out . ( yellow : vout, 0. 5 v/div, green : on/off, 2 v/div , 2ms/div ) figure 16 : turn on delay time at remote on 12vin, 1.8 v/ 2 0 a out . ( yellow : vout, 0. 5 v/div, green : on/off, 2 v/div , 2ms/div ) figure 17 : turn on delay time at remote on 12vin, 3.3 v/2 0 a out . ( yellow : vout, 1v/div, green : on/off, 2 v/div , 2ms/div ) figure 18 : turn on delay time at remote on 12vin, 5.0 v/2 0 a out . ( yellow : vout, 2v/div, green : on/off, 2 v/div , 2 ms/div )
ds_ d cl 12s0a 0s 2 0n fa _11152012 e - mail : dcdc @ d elta.com.tw http://www.deltaww.com/dcdc p 7 electrical character istics curves figure 19 : transient response to dynamic load change at 2.5 a/s from 50 % ~ 10 0% ~5 0% of io, max at 7 vin, 0.69 vout (cout = 1uf ceramic, 47uf *2 + 10f ceramic ) yellow : vout, 0.2v/div, 100us/div figure 20 : transient response to dynamic load change at 2.5 a/s from 50% ~ 100% ~50% of io, max at 12 vin, 1.8 vout (c out = 1uf ceramic, 47uf*2 + 10f ceramic ) yellow : vout, 0.2v/div, 100us/div figure 21 : transient response to dynamic load change at 2.5 a/s from 50% ~ 100% ~50% of io, max at 12 vin, 3.3 vout (cout = 1uf ceramic, 47uf*2 + 10f ceramic ) yellow : vout, 0.2v/div, 100us/div figure 2 2 : transient response to dynamic load change at 2.5 a/s from 50% ~ 100% ~50% of io, max at 12 vin, 5 vout (cout = 1uf ceramic, 47uf*2 + 10f ceramic ) yellow : vout, 0.2v/div, 100us/div
ds_ d cl 12s0a 0s 2 0n fa _11152012 e - mail : dcdc @ d elta.com.tw http://www.deltaww.com/dcdc p 8 electrical character istics cu rves (con.) figure 2 3 : tracking func ti on, vtracking=6v, vout= 5.0v, full load yellow : vout, (1v/div), green: tracking, (1v/div) , 500us/div figure 2 5 : tracking func ti on, vtracking= 0.8 v, vout= 0.69 v, full load y ellow: vout, 0.2v/div, green : tracking, 0.2v/div, 1ms/div figure 2 4 : tracking func ti on, vtracking=6v, vout= 5.0v, full load yellow : vout, (1v/div), green: tracking, (1v/div) , 10ms/div figure 26 : tracking func ti on, vtracking= 0.8 v, vout= 0.69 v, f ull load yellow: vout, 0.2v/div, green : tracking, 0.2v/div, 5ms/div
ds_ d cl 12s0a 0s 2 0n fa _11152012 e - mail : dcdc @ d elta.com.tw http://www.deltaww.com/dcdc p 9 t est configurations figure 27 : input reflected - ripple current test setup note: use a 10f and 1f capacitor. scope measurement should be made using a bnc connector. figure 28 : peak - peak output noise and startup transient measurement test setup. figure 29 : output voltage and efficiency measuremen t test setup note: all measurements are taken at the module terminals. when the module is not soldered (via socket), place kelvin connections at module terminals to avoid measurement errors due to contact resistance. design considerations input source impedance to maintain low noise and ripple at the input voltage, it is critical to use low esr capacitors at the input to the module. a highly inductive source can affect the stability of the module. an input capacitance must be placed close to the modules input pins to filter ripple current and ensure module stability in the presence of inductive traces that supply the input voltage to the module. safety considerations for safety - agency approval the power module must be installed in compliance with the spacing and separation requirements of the end - use safety agency standards. for the converter output to be considered meeting the requirements of safety extra - low voltage (selv), the input must meet selv requirements. the power module has extra - low voltage (elv) outputs when all inputs are elv. the input to these units is to be provided with a fast acting fuse with a maximum rating of 30 a in the positive input lead. v i vo gnd % 100 ) ( ? ? ? ? ii vi io vo ? design considerations input source impedance to maintain low noise and ripple at the input voltage, it is critical to use low esr capacitors at the input to the module. a highly inductive source c an affect the stability of the module. an input capacitance must be placed close to the modules input pins to filter ripple current and ensure module stability in the presence of inductive traces that supply the input voltage to the module. design considerations input source impedance to maintain low noise and ripple at the input voltage, it is critical to use low esr capacitors at the input to the module. a highly inductive source c an affect the stability of the module. an input capacitance must be placed close to the modules input pins to filter ripple current and ensure module stability in the presence of inductive traces that supply the input voltage to the module.
ds_ d cl 12s0a 0s 2 0n fa _11152012 e - mail : dcdc @ d elta.com.tw http://www.deltaww.com/dcdc p 10 fea tures descriptions remote on/off the dcl series power modules have an on/off pin for remote on/off operation. both positive and negative on/off logic options are available in the dc l series power modules. for positive logic module, connect an open coll ector (npn) transistor or open drain (n channel) mosfet between the on/off pin and the gnd pin (see figure 30). positive logic on/off signal turns the module on during the logic high and turns the module off during the logic low. when the positive on/off f unction is not used, leave the pin floating or tie to vin (module will be on). for negative logic module, the on/off pin is pulled high with an external pull - up 5k resistor (see figure 31). negative logic on/off signal turns the module off during logic h igh and turns the module on during logic low. if the negative on/off function is not used, leave the pin floating or tie to gnd. (module will be on) figure 30 : positive remote on/off implementation figure 31 : negative remote on/off implementation input under voltage lockout at input voltages below the input under voltage lockout limit, the module operation is disabled. the module will begin to operate at an input voltage above the under voltage lockout turn - on threshold. over - current protection to provide protection in an output over load fault condition, the unit is equipped with internal over - current protection. when the over - current protection is trigge red, the unit enters hiccup mode. the units operate normally once the fault condition is removed. remote sense the dc l provide vo remote sensing to achieve proper regulation at the load points and reduce effects of distribution losses on output line. in the event of an open remote sense line, the module shall maintain local sense regulation through an internal resistor. the module shall correct for a total of 0.5v of loss. the remote sense line impedance shall be < 10 ? . figure 32 : effective circuit co nfiguration for remote sense operation vo o n/o ff v in gnd q1 rl i o n /o f f vo on/off vin gnd q1 rl rpull- up i o n /o ff vo sense vin gnd rl distribution losses distribution losses distribution losses distribution losses
ds_ d cl 12s0a 0s 2 0n fa _11152012 e - mail : dcdc @ d elta.com.tw http://www.deltaww.com/dcdc p 11 features description s (con.) output voltage programming the output voltage of the dcl can be programmed to any voltage between 0.69vdc and 5 .5 vdc by connecting one r esistor (shown as rtrim in figure 33) between the trim and gnd pins of the module. without this external resistor, the output voltage of the module is 0.69 vdc. to calculate the value of the resistor rtrim for a particular output voltage vo, please use the following equation: rtrim is the external resistor in k vo is the desired output voltage. for example, to program the output voltage of the dc l module to 5.0vdc, rtrim is calculated as follows: fi gure 33 : circuit configulation for programming output voltage using an external resister. table 1 provides rtrim values required for some common output voltages. by using a 0.5% tolerance trim resistor with a tc of 100ppm, a set point tolerance of 1.5% can be achieved as specified in the electrical specification. c ertain restrictions apply on the output voltage set point depending on the input voltage. these are shown in the output voltage vs. input volta ge set point area plot in fig. 3 4. the upper limit curve shows that for output voltages of 0.9v and lower, the i nput voltage must be lower than the maximum of 14v. the lower limit curve shows that for output voltages of 3.3v and higher, the input voltage needs to be larger than the minimum of 4.5v figure 34 : output voltage vs input voltage setpoint area plot showing limits were the output can be set for different.input voltage. ? ? ? ? ? ? ? ? ? k vo rtrim 69 . 0 9 . 6 ? ? ? ? ? ? ? ? ? ? ? k k rtrim 601 . 1 69 . 0 0 . 5 9 . 6
ds_ d cl 12s0a 0s 2 0n fa _11152012 e - mail : dcdc @ d elta.com.tw http://www.deltaww.com/dcdc p 12 feature descriptions (con.) voltage margining output voltage margining can be implemented in the dc l modules by connecting a resistor, r margin - up, from the trim pin to the ground pin for margining - up the output voltage and by connecting a resistor, rmargin - down, from the trim pin to the output pin for margining - down. figure 35 shows the circuit configuration for output voltage margining. if unused, leave the trim pin unconnected. a calculation tool is available from the evaluation procedure which computes the values of rmargin - up and rmargin - down for a specific output voltage and margin percentage. figure 3 5 : circuit configuration for output voltage margining output voltage seq uencing the dcl 12v 20 a modules include a sequencing feature, ez - sequence that enables users to implement various types of output voltage sequencing in their applications. this is accomplished via an additional sequencing pin. when not using the sequencin g feature, either tie the seq pin to vin or leave it unconnected. when an analog voltage is applied to th e seq pin, the output voltage tracks this voltage until the output reaches the set - point voltage. the final value of the seq voltage must be set higher than the set - point voltage of the module. the output voltage follows the voltage on the seq pin on a one - to - one basis. by connecting multiple modules together, multiple modules can track their output voltages to the voltage applied on the seq pin. for proper voltage sequencing, first, input voltage is applied to the module. the on/off pin of the module is le ft unconnected (or tied to gnd for negative logic modules or tied to vin for positive logic modules) so that the module is on by default. after applying input voltage to the module, a minimum 10msec delay is required before applying voltage on the seq pin. this delay gives the module enough time to complete its internal power - up soft - start cycle. during the delay time, the seq pin should be held close to ground (nominally 50mv 20 mv). this is required to keep the internal op - amp out of saturation thus pre venting output overshoot during the start of the sequencing ramp. by selecting resistor r1 (see figure. 37) according to the following equation figure 36 : sequential start - up the voltage a t the sequencing pin will be 50mv when the sequencing signal is at zero. ? ? ? ? ? ? ? ? ? 05 . 0 24950 1 vin r
ds_ d cl 12s0a 0s 2 0n fa _11152012 e - mail : dcdc @ d elta.com.tw http://www.deltaww.com/dcdc p 13 feature descriptions (con.) after the 10msec delay, an analog voltage is appli ed to the seq pin and the output voltage of the module will track this voltage on a one - to - one volt bases until the output reaches the set - point voltage. to initiate simultaneous shutdown of the modules, the seq pin voltage is lowered in a controlled manne r. the output voltage of the modules tracks the voltages below their set - point voltages on a one - to - one basis. a valid input voltage must be maintained until the tracking and output voltages reach ground potential. when using the ez - sequencetm feature to control start - up of the module, pre - bias immunity during startup is disabled. the pre - bias immunity feature of the module relies on the module being in the diode - mode during start - up. when using the ez - sequencetm feature, modules goes through an internal s et - up time of 10msec, and will be in synchronous rectification mode when the voltage at the seq pin is applied. this will result in the module sinking current if a pre - bias voltage is present at the output of the module. figure 37 : circuit showing connec tion of the sequencing signal to the seq pin. simultaneous simultaneous tracking (figure 41) is implemented by using the track pin. the objective is to minimize the voltage difference between the power supply outputs during power up and down. power good the dc l modules provide a power good (pgood) signal that is implemented with an open - drain output to indicate that the output voltage is within the regulation limits of the power module. the pgood signal will be de - asserted to a low state if any cond ition such as over temperature, over current or loss of regulation occurs that would result in the output voltage going 10% outside the set point value. the pgood terminal should be connected through a pull up resistor (suggested value 100k) to a source of 5vdc or lower. monotonic start - up and shutdown the dc l 2 0 a modules have monotonic start - up and shutdown behavior for any combination of rated input voltage, output current and operating temperature range. synchronization the dc l 2 0 a modules can be s ynchronized using an external signal. details of the sync signal are provided in below table. if the synchronization function is not being used, leave the sync pin floating.
ds_ d cl 12s0a 0s 2 0n fa _11152012 e - mail : dcdc @ d elta.com.tw http://www.deltaww.com/dcdc p 14 thermal consideratio ns thermal management is an important part of the system design. to ensure proper, reliable operation, sufficient cooling of the power module is needed over the entir e temperature range of the module. convection cooling is usually the dominant mode of heat transfer. hence, the choice of equipment to characterize the thermal performance of the power module is a wind tunnel. thermal testing setup deltas dc/dc power m odules are characterized in heated vertical wind tunnels that simulate the thermal environments encountered in most electronics equipment. this type of equipment commonly uses vertically mounted circuit cards in cabinet racks in which the power modules are mounted. the following figure shows the wind tunnel characterization setup. the power module is mounted on a test pwb and is vertically positioned within the wind tunnel. thermal derating heat can be removed by increasing airflow over the module. to e nhance system reliability, the power module should always be operated below the maximum operating temperature. if the temperature exceeds the maximum module temperature, reliability of the unit may be affected. figure 38 : wind tunnel test setup thermal curves figure 39: temperature measurement location the allowed maximum hot spot temperature is defined at 1 17 figure 40 : output cur rent vs. ambient temperature and air velocity@vin=12v, vout=5.0v(either orientation) figure 41 : output current vs. ambient temperature and air velocity@vin=12v, vout=3.3v(either orientation) air flow module pwb 50.8(2.00") air velocity and ambient temperature sured below the module fancing pwb note: wind tunnel test setup figure dimensions are in millimeters and (inches) airflow 0 4 8 12 16 20 25 30 35 40 45 50 55 60 65 70 75 80 85 output current(a) ambient temperature ( ) dcl12s0a0s20nfa output current vs. ambient temperature and air velocity @vin = 12v, vo=5.0v (airflow from pin10 to pin8) 100lfm natural convection 200lfm 300lfm 400lfm 0 4 8 12 16 20 25 30 35 40 45 50 55 60 65 70 75 80 85 output current(a) ambient temperature ( ) dcl12s0a0s20nfa output current vs. ambient temperature and air velocity @vin = 12v, vo=3.3v (airflow from pin10 to pin8) 100lfm 400lfm natural convection 200lfm 300lfm
ds_ d cl 12s0a 0s 2 0n fa _11152012 e - mail : dcdc @ d elta.com.tw http://www.deltaww.com/dcdc p 15 thermal curves figure 42 : output current vs. ambient temperature and air velocity@vin=12v, vout=2.5v(either orientation) figure 43 : output current vs. ambient temperature and air velocity@vin=12v, vout=1.8v(either orientation) figure 44 : output current vs. ambient temperature and air velocity@vin= 12 v, vout= 1.2 v(either orientation) thermal curves figure 45 : output cur rent vs. ambient temperature and air velocity@vin= 7 v, vout= 0.69 v(either orientation) 0 4 8 12 16 20 25 30 35 40 45 50 55 60 65 70 75 80 85 output current(a) ambient temperature ( ) dcl12s0a0s20nfa output current vs. ambient temperature and air velocity @vin = 12v, vo=2.5v (airflow from pin10 to pin8) natural convection 100lfm 400lfm 200lfm 300lfm 0 4 8 12 16 20 25 30 35 40 45 50 55 60 65 70 75 80 85 output current(a) ambient temperature ( ) dcl12s0a0s20nfa output current vs. ambient temperature and air velocity @vin = 12v, vo=1.8v (airflow from pin10 to pin8) natural convection 100lfm 200lfm 300lfm 0 4 8 12 16 20 25 30 35 40 45 50 55 60 65 70 75 80 85 output current(a) ambient temperature ( ) dcl12s0a0s20nfa output current vs. ambient temperature and air velocity @vin = 12v, vo=1.2v (airflow from pin10 to pin8) natural convection 200lfm 100lfm 0 4 8 12 16 20 25 30 35 40 45 50 55 60 65 70 75 80 85 output current(a) ambient temperature ( ) dcl12s0a0s20nfa output current vs. ambient temperature and air velocity @vin = 7v, vo=0.69v (airflow from pin10 to pin8) natural convection 100lfm
ds_ d cl 12s0a 0s 2 0n fa _11152012 e - mail : dcdc @ d elta.com.tw http://www.deltaww.com/dcdc p 16 pick and place locat ion recommended pad lay out surface - mount tape & reel
ds_ d cl 12s0a 0s 2 0n fa _11152012 e - mail : dcdc @ d elta.com.tw http://www.deltaww.com/dcdc p 17 lead (sn/pb) process recommend te mp. profile note: the temperature refers to the pin of dc l , measured on the pin vout joint. lead free (sac) proc ess recommend temp. profile note: the tempe rature refers to the pin of dc l , measured on the pin vout joint . . temp . time 150 200 90~120 sec. time limited 75 sec. above 220 220 preheat time ramp up max. 3 ramp down max. 4 peak temp. 240 ~ 245 25
ds_ d cl 12s0a 0s 2 0n fa _11152012 e - mail : dcdc @ d elta.com.tw http://www.deltaww.com/dcdc p 18 mechanical drawin g
ds_ d cl 12s0a 0s 2 0n fa _11152012 e - mail : dcdc @ d elta.com.tw http://www.deltaww.com/dcdc p 19 p art numbering system dc l 12 s 0a0 s 2 0 n f a product series input voltage numbers of outputs output voltage package type output current on/off logi c option code dct - 3a d c s - 6a d c m - 1 2 a d c l - 20 a 04 - 2. 4 ~5.5v 1 2 C 4.5 ~14v s - single 0a0 - programmable s - smd 03 - 3a 06 - 6a 1 2 - 1 2 a 20 - 20 a n - negative p - positive f - rohs 6/6 (lead free) a - standard fun c tion model list model name packaging input voltage output voltage output current efficiency 12 vin, 5 vdc @ 2 0 a d cl 12 s0a0s 2 0n fa smd 4.5v ~ 14 vdc 0. 69 v~ 5. 0 vdc 2 0 a 9 3 .0 % contact: www.deltaww.com/dcdc usa: telephone: east coast: 978 - 65 6 - 3993 west coast: 510 - 668 - 5100 fax: (978) 656 3964 email: dcdc@delta - corp.com europe: telephone: +31 - 20 - 655 - 0967 fax: +31 - 20 - 655 - 0999 email: dcdc@delta - es. com asia & the rest of world: telephone: +886 3 4526107 x6220 ~6224 fax: +886 3 4513485 email: dcdc@delta.com.tw warranty delta offers a two ( 2) year limited warranty. complete warranty information is listed on our web site or is available upon request from delta. information furnished by delta is believed to be accurate and reliable. however, no responsibility is assumed by delta for its use, nor for any infringements of patents or other rights of third parties, which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of delta. delta reserves the right to revise these specifications at any time, without notice .

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